Senior high-speed analog layout engineer
IrvineChelsea Search Group
...Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred) • At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16) • Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit [...]
Category IT & Telecommunications