Senior analog design engineer
Santa Claraadecco
...IC device physics, spice models, ESD, latch-up, and manufacturing technology are also required.· Proficient in the use of Cadence's IC design environment (Virtuoso Schematic/Layout), analog circuit simulation (Spectre/ADE), and digital RTL design (System Verilog).· Knowledge of mixed mode simulation (Cadence AMS [...]
Category Engineering & Architecture
20 days ago in Adecco